An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Optimal design of synchronous circuits using software pipelining techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Routability driven floorplanner with buffer block planning
Proceedings of the 2002 international symposium on Physical design
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An integrated floorplanning with an efficient buffer planning algorithm
Proceedings of the 2003 international symposium on Physical design
Floorplanning of pipelined array modules using sequence pairs
Proceedings of the 2003 international symposium on Physical design
Porosity aware buffered steiner tree construction
Proceedings of the 2003 international symposium on Physical design
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Flip-Flop and Repeater Insertion for Early Interconnect Planning
Proceedings of the conference on Design, automation and test in Europe
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new approach to latency insensitive design
Proceedings of the 41st annual Design Automation Conference
Floorplan assisted data rate enhancement through wire pipelining: a real assessment
Proceedings of the 2005 international symposium on Physical design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Microarchitecture evaluation with floorplanning and interconnect pipelining
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Processing Rate Optimization by Sequential System Floorplanning
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Formal methods for scheduling of latency-insensitive designs
EURASIP Journal on Embedded Systems
Microarchitecture configurations and floorplanning co-optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Large Systems-on-Chip (SoC) in advanced technologies run at such high frequencies that the time-of-flight of signals connecting two distant pins in the layout can be higher than the clock period. In order to avoid performance penalties wires are pipelined using latches. However the throughput of the system may be altered due to the presence of loops in the logic netlist. In this paper we address the problem of floorplanning a large design with interconnect pipelining and inserting throughput in the cost function of the floorplanning algorithm. The throughput results obtained on a series of benchmarks are then validated using a simple router that places flipflops along the nets built with an heuristical minimum rectilinear steiner tree.