A new approach to the rectilinear Steiner tree problem
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Modeling and minimization of routing congestion
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
Proceedings of the 40th annual Design Automation Conference
A New Effective Congestion Model in Floorplan Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2004 international symposium on Physical design
A buffer planning algorithm with congestion optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fast buffer planning and congestion optimization in interconnect-driven floorplanning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Interconnect-driven floorplanning by searching alternative packings
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A buffer planning algorithm based on dead space redistribution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An effective buffer planning algorithm for IP based fixed-outline SOC placement
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An accurate and efficient probabilistic congestion estimation model in x architecture
Proceedings of the 2007 international workshop on System level interconnect prediction
An enhanced congestion-driven floorplanner
WSEAS Transactions on Circuits and Systems
Improved performance and yield with chip master planning design methodology
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Congestion-driven floorplanning with module reshaping
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Handling routability in floorplan design with twin binary trees
Integration, the VLSI Journal
Buffer planning for IP placement using sliced-LFF
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
A new buffer planning algorithm based on room resizing
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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In traditional floorplanners, area minimization is an important issue. However, due to the recent advances in VLSI technology, the number of transistors in a design are increasing rapidly and so are their switching speeds. This has increased the importance of interconnect delay and routability in the overall performance of a circuit. We should consider interconnect planning, buffer planning and routability as early as possible. In this paper, we study and implement a routability-driven floorplanner with congestion estimation and buffer planning. Our method is based on a simulated annealing approach that is divided into two phases: the area optimization phase and the congestion optimization phase. In the area optimization phase, modules are roughly placed according to the total area and wirelength. In the congestion optimization phase, a floorplan will be evaluated by its area, wirelength, congestion and routability. We assume that every buffer should be inserted at a flexible interval from each other for long enough wires and probabilistic analysis is performed to compute the congestion information taken into accounts the constraints in buffer locations. Our approach is able to reduce the average number of wires at the congested areas and allow more feasible insertions of buffers to satisfy the delay constraints without having much penalty in increasing the area of the floorplan.