Introduction to algorithms
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Routability driven floorplanner with buffer block planning
Proceedings of the 2002 international symposium on Physical design
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An integrated floorplanning with an efficient buffer planning algorithm
Proceedings of the 2003 international symposium on Physical design
A buffer planning algorithm based on dead space redistribution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
A buffer planning algorithm with congestion optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Buffer allocation algorithm with consideration of routing congestion
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Buffer Planning Algorithm Based on Partial Clustered Floorplanning
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Congestion prediction in early stages
Proceedings of the 2005 international workshop on System level interconnect prediction
Is probabilistic congestion estimation worthwhile?
Proceedings of the 2005 international workshop on System level interconnect prediction
Congestion prediction in floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Area reduction by deadspace utilization on interconnect optimized floorplan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An accurate and efficient probabilistic congestion estimation model in x architecture
Proceedings of the 2007 international workshop on System level interconnect prediction
Optimizing wirelength and routability by searching alternative packings in floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Congestion prediction in early stages of physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And the detail locating of the blocks in their rooms can be implemented for each iterations during the annealing process to favor the later buffer planning. The buffer insertion will affect the possible routes as well the congestion of the packing. The congestion estimation in this paper takes the buffer insertion into account. So we devise a buffer planning algorithm to allocate the buffer into tiles with congestion information considered. The buffer allocation problem is formulated into a net flow problem and the buffer allocation can be handled as an integral part in the floorplanning process. Since there is more freedom for floorplan optimization, the floorplanning algorithm integrated with buffer planning can result in better performance and chip area.