Optimizing wirelength and routability by searching alternative packings in floorplanning

Authors:
Chiu-Wing Sham;Evangeline F. Y. Young;Hai Zhou
Affiliations:
The Hong Kong Polytechnic University, Kowloon, Hong Kong;The Chinese University of Hong Kong, NT, Hong Kong SAR;Northwestern University, Evanston, IL
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2008

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Abstract

Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the interconnect cost of a floorplan by searching alternative packings. If a packing contains a rectangular bounding box of a group of modules, we can rearrange the blocks in the bounding box to obtain a new floorplan with the same area, but possibly with a smaller interconnect cost. Experimental results show that we can reduce the interconnect cost of a packing without any penalty in area.