Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Arbitrary convex and concave rectilinear block packing using sequence-pair
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Module placement for analog layout using the sequence-pair representation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
An enhanced perturbing algorithm for floorplan design using the O-tree representation
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Block placement with symmetry constraints based on the O-tree non-slicing representation
Proceedings of the 37th Annual Design Automation Conference
Fast evaluation of sequence pair in block placement by longest common subsequence computation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A new efficient method for substrate-aware device-level placement (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Consistent floorplanning with super hierarchical constraints
Proceedings of the 2001 international symposium on Physical design
ECBL: an extended corner block list with solution space including optimum placement
Proceedings of the 2001 international symposium on Physical design
Rectilinear block packing using O-tree representation
Proceedings of the 2001 international symposium on Physical design
Device-level placement for analog layout: an opportunity for non-slicing topological representations
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
VLSI floorplanning with boundary constraints based on corner block list
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Module placement with boundary constraints using the sequence-pair representation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list
Proceedings of the 38th annual Design Automation Conference
Constrained polygon transformations for incremental floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
Modeling non-slicing floorplans with binary trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Color permutation: an iterative algorithm for memory packing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Constrained "Modern" Floorplanning
Proceedings of the 2003 international symposium on Physical design
Floorplanning of pipelined array modules using sequence pairs
Proceedings of the 2003 international symposium on Physical design
Fishbone: a block-level placement and routing scheme
Proceedings of the 2003 international symposium on Physical design
An optimum placement search algorithm based on extended corner block list
Journal of Computer Science and Technology
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Hierarchical Data Visualization Using a Fast Rectangle-Packing Algorithm
IEEE Transactions on Visualization and Computer Graphics
Proceedings of the 2004 international symposium on Physical design
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Innovate or perish: FPGA physical design
Proceedings of the 2004 international symposium on Physical design
A device-level placement with multi-directional convex clustering
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Practical slicing and non-slicing block-packing without simulated annealing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Stairway compaction using corner block list and its applications with rectilinear blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-Million Gate FPGA Physical Design Challenges
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Abstraction and optimization of consistent floorplanning with pillar block constraints
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Space-planning: placement of modules with controlled empty area by single-sequence
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On handling arbitrary rectilinear shape constraint
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Multi-level placement with circuit schema based clustering in analog IC layouts
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An orthogonal simulated annealing algorithm for large floorplanning problems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ant colony system application to macrocell overlap removal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
This paper presents a cost-effective area-IO DRAM A CAD Tool and Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
Fixed-outline floorplanning based on common subsequence
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast evaluation of bounded slice-line grid
Journal of Computer Science and Technology
Simultaneous design and placement of multiplexed chemical processing systems on microchips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
Proceedings of the 2006 international workshop on System-level interconnect prediction
FastPlace 2.0: an efficient analytical placer for mixed-mode designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Signal-path driven partition and placement for analog circuit
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multi-level placement for large-scale mixed-size IC designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Using red-black interval trees in device-level analog placement with symmetry constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
LFF algorithm for heterogeneous FPGA floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Microarchitecture evaluation with floorplanning and interconnect pipelining
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Effective linear programming based placement methods
Proceedings of the 2006 international symposium on Physical design
How does partitioning matter for 3D floorplanning?
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Wirelength optimization by optimal block orientation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design automation issues for biofluidic microchips
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Layout-driven architecture synthesis for high-speed digital filters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
A bijection between permutations and floorplans, and its applications
Discrete Applied Mathematics
Block placement to ensure channel routability
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A stable fixed-outline floorplanning method
Proceedings of the 2007 international symposium on Physical design
A fast algorithm for rectilinear block packing based on selected sequence-pair
Integration, the VLSI Journal
Fast wire length estimation by net bundling for block placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new heuristic algorithm for rectangle packing
Computers and Operations Research
Bin Packing in Multiple Dimensions: Inapproximability Results and Approximation Schemes
Mathematics of Operations Research
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
Integration, the VLSI Journal
Fixed-outline floorplanning using robust evolutionary search
Engineering Applications of Artificial Intelligence
Power-density aware floorplanning for reducing maximum on-chip temperature
MOAS'07 Proceedings of the 18th conference on Proceedings of the 18th IASTED International Conference: modelling and simulation
Optimizing wirelength and routability by searching alternative packings in floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Microarchitecture configurations and floorplanning co-optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Constraint-driven floorplanning based on genetic algorithm
CEA'07 Proceedings of the 2007 annual Conference on International Conference on Computer Engineering and Applications
Floorplan considering interconnection between different clock domains
ICC'07 Proceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 11
3-D floorplanning using labeled tree and dual sequences
Proceedings of the 2008 international symposium on Physical design
Symmetry-aware placement with transitive closure graphs for analog layout design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
An improved particle swarm optimizer for placement constraints
Journal of Artificial Evolution and Applications - Particle Swarms: The Second Decade
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Heuristic approaches for the two- and three-dimensional knapsack packing problem
Computers and Operations Research
Block flipping and white space distribution for wirelength minimization
Integration, the VLSI Journal
Linear constraint graph for floorplan optimization with soft blocks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Thermal optimization in multi-granularity multi-core floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A Relocation Method for Circuit Modifications
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Energy/area/delay tradeoffs in the physical design of on-chip segmented bus architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evolving reusable 3d packing heuristics with genetic programming
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
Provably near-optimal solutions for very large single-row facility layout problems
Optimization Methods & Software - GLOBAL OPTIMIZATION
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A tree based novel representation for 3D-block packing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power-density aware floorplanning for reducing maximum on-chip temperature
MS '07 The 18th IASTED International Conference on Modelling and Simulation
A Discrete PSO for Multi-objective Optimization in VLSI Floorplanning
ISICA '09 Proceedings of the 4th International Symposium on Advances in Computation and Intelligence
Multi-objective rectangular packing problem and its applications
EMO'03 Proceedings of the 2nd international conference on Evolutionary multi-criterion optimization
An effective approach for large scale floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Hybrid algorithm for floorplanning using B*-tree representation
IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
Multi-objective floorplanning based on fuzzy logic
FSKD'09 Proceedings of the 6th international conference on Fuzzy systems and knowledge discovery - Volume 4
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
Integration, the VLSI Journal
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
SEU-aware resource binding for modular redundancy based designs on FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Physically-aware exploitation of component reuse in a partially reconfigurable architecture
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Regularity-oriented analog placement with diffusion sharing and well island generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Regularity-constrained floorplanning for multi-core processors
Proceedings of the 2011 international symposium on Physical design
E-beam lithography stencil planning and optimization with overlapped characters
Proceedings of the 2011 international symposium on Physical design
Floorplacement for partial reconfigurable FPGA-based systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
Floorplanning with IR-drop consideration
ICOSSSE'05 Proceedings of the 4th WSEAS/IASME international conference on System science and simulation in engineering
Floorplanning algorithm for multiple clock domains
ICOSSSE'05 Proceedings of the 4th WSEAS/IASME international conference on System science and simulation in engineering
Floorplanning method based on liner programming
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement for immunity of transient faults in cell-based design of nanometer circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast substrate noise aware floorplanning for mixed signal SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement constraints and macrocell overlap removal using particle swarm optimization
ANTS'06 Proceedings of the 5th international conference on Ant Colony Optimization and Swarm Intelligence
Packing problems with soft rectangles
HM'06 Proceedings of the Third international conference on Hybrid Metaheuristics
A corner stitching compliant B*-tree representation and its applications to analog placement
Proceedings of the International Conference on Computer-Aided Design
SEMCCO'11 Proceedings of the Second international conference on Swarm, Evolutionary, and Memetic Computing - Volume Part I
Resource augmentation in two-dimensional packing with orthogonal rotations
Operations Research Letters
Practically scalable floorplanning with voltage island generation
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Multi-bend bus-driven floorplanning considering fixed-outline constraints
Integration, the VLSI Journal
Multiobjective layout optimization of robotic cellular manufacturing systems
Computers and Industrial Engineering
Multi objective integrated layout design problem
SEMCCO'12 Proceedings of the Third international conference on Swarm, Evolutionary, and Memetic Computing
Practicality on placement given by optimality of packing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Variable-Order Ant System for VLSI multiobjective floorplanning
Applied Soft Computing
E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system
Proceedings of the 50th Annual Design Automation Conference
Bus-driven floorplanning with thermal consideration
Integration, the VLSI Journal
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
Regularity-constrained floorplanning for multi-core processors
Integration, the VLSI Journal
| Hi-index | 0.03 |
The earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is the introduction of a finite solution space which includes an optimal solution. This paper proposes such a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair. Searching this space by simulated annealing, hundreds of modules have been packed efficiently as demonstrated. For applications to VLSI layout, we attack the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement