Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis

Authors:
Dongku Kang;Yiran Chen;Kaushik Roy
Affiliations:
Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

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Abstract

As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for high-level synthesis. By evaluating power supply noise in the early design stage, the proposed method generates schedule and resource allocation with a floorplan such that the power supply noise is minimized. To achieve the goal, we formulated the problem using a genetic algorithm. Compared to designs that do not consider supply noise, the proposed methodology reduces power supply noise up to 44%.