On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
Clock and Power Gating with Timing Closure
IEEE Design & Test
Proceedings of the 2003 international symposium on Low power electronics and design
Energy-reliability trade-off for NoCs
Networks on chip
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
3D module placement for congestion and power noise reduction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partitioning-based approach to fast on-chip decap budgeting and minimization
Proceedings of the 42nd annual Design Automation Conference
Combined circuit and architectural level variable supply-voltage scaling for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel wavelet transform-based transient current analysis for fault detection and localization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power distribution techniques for dual VDD circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Wake-up protocols for controlling current surges in MTCMOS-based technology
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Timing-aware power noise reduction in layout
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Accurate power grid analysis with behavioral transistor network modeling
Proceedings of the 2007 international symposium on Physical design
Fast decap allocation based on algebraic multigrid
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Decoupling capacitor planning and sizing for noise and leakage reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Partitioning-based decoupling capacitor budgeting via sequence of linear programming
Integration, the VLSI Journal
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A unified methodology for power supply noise reduction in modern microarchitecture design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effective radii of on-chip decoupling capacitors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power supply noise aware workload assignment for multi-core systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance efficient placement for reducing transient power supply noise
Proceedings of the 2009 International Conference on Computer-Aided Design
Methodology for efficient substrate noise analysis in large-scale mixed-signal circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoupling capacitor planning with analytical delay model on RLC power grid
Proceedings of the Conference on Design, Automation and Test in Europe
An efficient decoupling capacitance optimization using piecewise polynomial models
Proceedings of the Conference on Design, Automation and Test in Europe
Reconfigurable ECO cells for timing closure and IR drop minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-objective module placement for 3-d system-on-package
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and reduction of supply noise fluctuations induced by embedded via-programming ROM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient distributed on-chip decoupling capacitors for nanoscale ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast algorithms for IR voltage drop analysis exploiting locality
Proceedings of the 48th Design Automation Conference
Decoupling for power gating: sources of power noise and design strategies
Proceedings of the 48th Design Automation Conference
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We investigate the problem of decoupling capacitance (decap) allocation for power supply noise suppression at floorplan level. First, we assume that a floorplan is given and consider the decap placement as a postfloorplan step. Second, we consider the decap placement as an integral part of a floorplanning methodology (noise-aware floorplanning). In both cases, the objective is to minimize the floorplan area while suppressing the power supply noise below the specified limit. Experimental results on MCNC benchmark circuits show that, for postfloorplan decap placement, the white space allocated for decap is about 6%-9% of the chip area for the 0.25-μm technology. The power-supply noise is kept below the specified limit. Compared to postfloorplan approach, the peak power-supply noise can be reduced by as much as 40% and the decap budget can be reduced by as much as 21% by using noise-aware floorplanning methodology. The total area is also reduced due to the reduced total decap budget gained from reduced power supply noise