The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Dynamic voltage scaling on a low-power microprocessor
Proceedings of the 7th annual international conference on Mobile computing and networking
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A unified methodology for power supply noise reduction in modern microarchitecture design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, we propose an integrated architectural and physical planning approach to minimize the current surge in high-performance clock-gated microprocessors. In our approach, we use priority assignment optimization (PAO) and dynamic functional unit (FU) selection (DFS) to balance current demand in the floorplan. Two complementary methods--FU ordering with submodule design and issue pattern management--are also proposed to enhance the above techniques. Experimental results show that at the 0.18-µm technology node, the PAO can reduce the peak noise by 11.75% and consequently, the decoupling capacitance (Decap) requirement by 24.22% without any degradation in instructions per cycle (IPC). Moreover, an enhanced DFS reduces the peak noise by 13.39% as well as Decap requirement by 29.58%. Experiments at the 90-nm technology node show that our methodology can further reduce the peak noise and the Decap requirement by 16.57% and 44.85% with PAO, or 18.16% and 47.58% with DFS. We also show that our approach does not increase the clock period for 0.18-µm technology and beyond.