Zero-cycle loads: microarchitecture support for reducing load latency
Proceedings of the 28th annual international symposium on Microarchitecture
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Inductive Noise Reduction at the Architectural Level
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Proceedings of the 2003 international symposium on Low power electronics and design
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 2004 international symposium on Low power electronics and design
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Decoupling capacitor planning and sizing for noise and leakage reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Power Grid Physics and Implications for CAD
IEEE Design & Test
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A unified methodology for power supply noise reduction in modern microarchitecture design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DCG: deterministic clock-gating for low-power microprocessor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
VLSI/PCB placement with obstacles based on sequence pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous power supply planning and noise avoidance in floorplan design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal placement of power-supply pads and pins
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this article, we propose a design methodology using two complementary techniques to address high-frequency inductive noise in the early design phase of a microprocessor. First, we propose a noise-aware floorplanning technique that uses microarchitectural profile information to create noise-aware floorplans. Second, we present the design of a dynamic inductive-noise controlling mechanism at the microarchitectural level, which limits the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the access patterns of microarchitectural modules, our mechanism can effectively limit simultaneous switching activity of close-by modules, thereby leveling voltage ringing at local power-pins. Compared to prior art, our di/dt alleviation technique is the first that takes the processor's floorplan, as well as its power-pin distribution, into account to provide a finer-grained control with minimal performance degradation. Based on the evaluation results using 2D floorplans, we show that our techniques can significantly improve inductive noise induced by current demand variation and reduce the average current variability by up to 7 times, with an average performance overhead of 4.0%. In addition, our floorplan reduces the noise margin violations using our noise-aware floorplan by an average of 56.3% while reducing the decap budget by 28%.