Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Impedance characteristics of power distribution grids in nanoscale integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power grid analysis using random walks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A microarchitecture-based framework for pre- and post-silicon power delivery analysis
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast algorithms for IR voltage drop analysis exploiting locality
Proceedings of the 48th Design Automation Conference
Efficient algorithms for fast IR drop analysis exploiting locality
Integration, the VLSI Journal
Distributed power network co-design with on-chip power supplies and decoupling capacitors
Proceedings of the System Level Interconnect Prediction Workshop
IR-drop in on-chip power distribution networks of ICs with nonuniform power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
An accurate analysis of supply noise in power distribution networks is essential to ensure reliable performance in high-performance designs. Recently, several analysis and optimization techniques for on-chip power grid networks have been proposed. However, all of these approaches assume a particular simplified model or behavior of the complex power delivery network. This article describes the first detailed, full-die, dynamic model of an Intel Pentium IV microprocessor design. The authors justify this model from the ground up, starting with a full-wave model and then using increasingly larger, but less detailed models, with only the irrelevant elements removed at each step. Using these models, the authors show that there is little impact of on-die inductance in such a design, and that package-die cosimulation is critical to understanding the grid's resonant properties. The authors also show that transient supply noise is sensitive to the nonuniform decoupling-capacitor (decap) distribution and that supply drop locality is a tight function of frequency and package-die resonance. All of these points have an impact on the kind of analysis and optimization required from CAD.