Discrete Applied Mathematics
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Proceedings of the 2004 international symposium on Low power electronics and design
Towards a software approach to mitigate voltage emergencies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Power Grid Physics and Implications for CAD
IEEE Design & Test
BLoG: post-silicon bug localization in processors using bug localization graphs
Proceedings of the 47th Design Automation Conference
On-die power grids: the missing link
Proceedings of the 47th Design Automation Conference
Automated di/dt stressmark generation for microprocessor power delivery networks
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Power grid effects and their impact on-die
Proceedings of the International Conference on Computer-Aided Design
AUDIT: Stress Testing the Automatic Way
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Performance boosting under reliability and power constraints
Proceedings of the International Conference on Computer-Aided Design
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Variations in power supply voltage, which is a function of the power delivery network and dynamic current consumption, can affect circuit reliability. Much work has been done to understand power delivery robustness during both the design phase as well as the post-silicon validation phase. Methods applicable at the design phase typically synthesize worst-case current waveforms based on simple current constraints but fail to provide corresponding instruction streams due to their ignorance of the functional aspects of the machine and hence cannot be validated. Approaches used for post-silicon validation are not useful during design, and either rely heavily on available test content which can come from power, performance, or defect testing, and hence are limited in validation potential or employ manually-crafted tests aimed at power delivery, and hence are highly labor-intensive. In this paper, we provide a novel approach to construct processor current waveforms to induce significant droops while at the same time producing instruction streams to achieve those waveforms. We solve the pre-silicon current stimulus generation problem as an optimization problem. The modular framework in this paper utilizes microarchitectural information, current consumption estimates of fine-grained microarchitectural components and a pre-characterized power delivery network to obtain significant droop-inducing current waveforms. The paper further discusses techniques to convert operations associated with these generated waveforms to functional instruction streams. Silicon measurements of such tests run on an industrial microprocessor validate the approach.