An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Proceedings of the 2003 international symposium on Low power electronics and design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 2004 international symposium on Low power electronics and design
Towards a software approach to mitigate voltage emergencies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A microarchitecture-based framework for pre- and post-silicon power delivery analysis
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Active management of timing guardband to save energy in POWER7
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
AUDIT: Stress Testing the Automatic Way
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
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Voltage droops resulting from inductive noise are common in state-of-the-art processors. Many of the techniques used to reduce energy consumption -- clock gating, power gating, process shrinks, and voltage reduction -- lead to increased voltage droops or increased sensitivity to voltage variations. Designers use voltage guardbands to minimize errors due to voltage fluctuations and inductive noise; however, this leads to lower performance because the voltage and frequency points are set to deal with voltage droops from a worst-case benchmark or stressmark. Although most applications do not approach the voltage droop caused by the stressmark, there is no mechanism to guarantee correct operation outside the tested range. In this paper, we examine floating-point issue throttling (FP throttling), a hardware technique that reduces worst-case voltage droop. By lowering the issue rate in the FP scheduler, the processor can significantly reduce the maximum voltage droop in the system. We show the impact of FP throttling on voltage droop, and translate this reduction in voltage droop to an increase in operating frequency (and hence increased performance) because an additional guardband is no longer required to guard against droops resulting from heavy FP usage. We then examine the impact of FP throttling and guardband reduction on the SPEC CPU2006 benchmarks and show that some benchmarks benefit from the frequency improvements with FP throttling while others suffer due to reduced FP throughput. Finally, we present two techniques to determine dynamically when to trade FP throughput for reduced voltage margin and increased frequency, and show performance improvements of up to 15% for CINT2006 benchmarks and up to 8% for CFP2006 benchmarks. Our studies are done on hardware in which FP units generate the worst-case voltage droop. The technique can be modified for architectures in which other units cause the worst droop.