The implications of shared data synchronization techniques on multi-core energy efficiency
HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
Power monitoring for mixed-criticality on a many-core platform
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
High performance and low power design techniques for ASIC and custom in nanometer technologies
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Parallel HEVC Decoding on Multi- and Many-core Architectures
Journal of Signal Processing Systems
Enabling accurate power profiling of HPC applications on exascale systems
Proceedings of the 3rd International Workshop on Runtime and Operating Systems for Supercomputers
MuMMI: multiple metrics modeling infrastructure for exploring performance and power modeling
Proceedings of the Conference on Extreme Science and Engineering Discovery Environment: Gateway to Discovery
Cooperative boosting: needy versus greedy power management
Proceedings of the 40th Annual International Symposium on Computer Architecture
Hierarchical power management for asymmetric multi-core in dark silicon era
Proceedings of the 50th Annual Design Automation Conference
ACM Transactions on Architecture and Code Optimization (TACO)
FDIO: a feedback driven controller for minimizing energy in I/O-intensive applications
HotStorage'13 Proceedings of the 5th USENIX conference on Hot Topics in Storage and File Systems
IA^3 '13 Proceedings of the 3rd Workshop on Irregular Applications: Architectures and Algorithms
OpenMP and MPI application energy measurement variation
E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
Easy, fast, and energy-efficient object detection on heterogeneous on-chip architectures
ACM Transactions on Architecture and Code Optimization (TACO)
Performance boosting under reliability and power constraints
Proceedings of the International Conference on Computer-Aided Design
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Modern microprocessors are evolving into system-on-a-chip designs with high integration levels, catering to ever-shrinking form factors. Portability without compromising performance is a driving market need. An architectural approach that's adaptive to and cognizant of workload behavior and platform physical constraints is indispensable to meeting these performance and efficiency goals. This article describes power-management innovations introduced on Intel's Sandy Bridge microprocessor.