The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design
Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design
Bobcat: AMD's Low-Power x86 Processor
IEEE Micro
Keep it straight: teaching placement how to better handle designs with datapaths
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Network flow based datapath bit slicing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
FF-bond: multi-bit flip-flop bonding at placement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Composite Cores: Pushing Heterogeneity Into a Core
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
High-performance gate sizing with a signoff timer
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Traditionally, synthesized application-specific integrated circuits (ASICs) have been slower and higher power than custom integrated circuits due to a variety of factors. This paper details how this gap has decreased in the past few years. ASICs have adopted higher performance and lower power design techniques with the aid of better CAD tool support. To improve productivity, many full custom designs have migrated to a semi-custom design methodology that is more amenable to the use of standard CAD tools and makes greater use of synthesis.