RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A two moment RC delay metric for performance optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
PERI: a technique for extending delay and slew metrics to ramp inputs
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing for cell-library-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing for large cell-based designs
Proceedings of the Conference on Design, Automation and Test in Europe
Gate sizing and device technology selection algorithms for high-performance industrial designs
Proceedings of the International Conference on Computer-Aided Design
The ISPD-2012 discrete cell sizing contest and benchmark suite
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple metric for slew rate of RC circuits based on two circuit moments
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Numerically Convex Forms and Their Application in Gate Sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design
High performance and low power design techniques for ASIC and custom in nanometer technologies
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Circuit and PD challenges at the 14nm technology node
Proceedings of the 2013 ACM international symposium on International symposium on physical design
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Fast and efficient lagrangian relaxation-based discrete gate sizing
Proceedings of the Conference on Design, Automation and Test in Europe
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Process and device scaling in late-CMOS technologies highlight leakage power as a critical challenge for the semiconductor industry. Careful gate sizing and Vth-swapping can reduce leakage, but prior optimizations based on convex or dynamic programming (i) are often based on unrealistic assumptions about circuit delay and slew propagation, (ii) fail to handle practical design rules such as transition time or load upper bounds, and (iii) do not scale well to input complexities when full extracted parasitics are available. Seeing substantial opportunities for improvement, we present a multi-threaded, stochastic optimization (Trident2.0) for gate sizing and Vth assignment to minimize leakage power subject to capacitance, slew and timing constraints. Scalability and high performance of Trident2.0 are validated on ISPD-2013 Gate Sizing Contest benchmarks.