Transistor Level Budgeting for Power Optimization
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
Gate sizing by Lagrangian relaxation revisited
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing analysis of computer hardware
IBM Journal of Research and Development
Transistor sizing for large combinational digital CMOS circuits
Integration, the VLSI Journal
iCOACH: A circuit optimization aid for CMOS high-performance circuits
Integration, the VLSI Journal
Statistical timing yield optimization by gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact transistor sizing based on iterative relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Unified Theory of Timing Budget Management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design
High-performance gate sizing with a signoff timer
Proceedings of the International Conference on Computer-Aided Design
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Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices and realistic timing models. The approach iteratively assigns signal slew targets to all source pins of the chip and chooses discrete layouts of minimum size preserving the slew targets. Using slew targets instead of delay budgets, accurate estimates for the input slews are available during the sizing step. Slew targets are updated by an estimate of the local slew gradient. To demonstrate the effectiveness, we propose a new heuristic to estimate lower bounds for the worst path delay. On average, we violate these bounds by 6%. A subsequent local search decreases this gap quickly to 2%. This two-stage approach is capable of sizing designs with more than 5.8 million cells within 2.5 hours and thus helping to decrease turn-around times of multi-million cell designs.