Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Introduction to nMOS & VLSI systems design
Introduction to nMOS & VLSI systems design
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Transistor sizing in CMOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Fundamentals of MOS digital integrated circuits
Fundamentals of MOS digital integrated circuits
Algorithms for automatic transistor sizing in CMOS digital circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Numerical Optimization of Computer Models
Numerical Optimization of Computer Models
Linear System Theory and Design
Linear System Theory and Design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Delay and power optimization in VLSI circuits
DAC '84 Proceedings of the 21st Design Automation Conference
Rule-based circuit optimization for cmos vlsi
Rule-based circuit optimization for cmos vlsi
LSS: a system for production logic synthesis
IBM Journal of Research and Development
A Rule-Based System for Optimizing Combinational Logic
IEEE Design & Test
PERT as an aid to logic design
IBM Journal of Research and Development
MINI: a heuristic approach for logic minimization
IBM Journal of Research and Development
A New Symbolic Channel Router: YACR2
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Efficient Approach to Gate Matrix Layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MIS: A Multiple-Level Logic Optimization System
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing for large cell-based designs
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
iCOACH is a two-pass iterative circuit optimizer which generates a polycell-based layout from a gate level description file and user-defined timing constraints. The first pass is to generate, place and route the cells and extract the interconnection parameters. The second pass optimizes the circuit at the transistor level and makes necessary layout adjustments including pitch-matchings. Although iCOACH has the layout style similar to the polycell approach, it is distinct in two important aspects. First, iCOACH does not rely on any fixed cell library. Instead iCOACH generated customized cells by invoking the circuit optimizer and performs the transistor-level optimization for both static and dynamic CMOS circuits and their layouts under realistic constraints. Secondly, although the cells in the same row are required to have the same height, different rows can have different heights to make circuit more compact. Dynamic circuits are used with a careful treatment on reliability issues related to charge sharing and noise margin, which has not been treated rigorously in the previous literature. An area-efficient polycell layout style is also introduced for dynamic CMOS circuits. A 4-bit ALU and a 32-bit adder examples are presented to demonstrate the capability of iCOACH.