The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Numerical recipes: the art of scientific computing
Numerical recipes: the art of scientific computing
DAC '83 Proceedings of the 20th Design Automation Conference
Delay and power optimization in VLSI circuits
DAC '84 Proceedings of the 21st Design Automation Conference
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
Delay and area optimization in standard-cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Algorithms for library-specific sizing of combinational logic
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Experiments with a performance driven module generator
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
iCOACH: A circuit optimization aid for CMOS high-performance circuits
Integration, the VLSI Journal
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The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.