Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Transistor sizing in CMOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Algorithms and Techniques for VLSI Layout and Synthesis
Algorithms and Techniques for VLSI Layout and Synthesis
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Timing verification using statically sensitizable paths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
Minimal delay interconnect design using alphabetic trees
DAC '94 Proceedings of the 31st annual Design Automation Conference
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power-delay characteristics of CMOS adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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