Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Experiments with a performance driven module generator
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Short-circuit power driven gate sizing technique for reducing power dissipation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
A power optimization method considering glitch reduction by gate sizing
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A practical gate resizing technique considering glitch reduction for low power design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
The sandbridge SB3011 platform
EURASIP Journal on Embedded Systems
Full custom low-power/high performance DDP-based Cobra-H64 cipher
Computers and Electrical Engineering
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Soft error-aware power optimization using gate sizing
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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