Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A new model for computation of probabilistic testability in combinational circuits
Integration, the VLSI Journal
Improved Techniques for Estimating Signal Probabilities
IEEE Transactions on Computers
IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Re-encoding sequential circuits to reduce power dissipation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Low power state assignment targeting two-and multi-level logic implementations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Estimation of circuit activity considering signal correlations and simultaneous switching
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A cell-based power estimation in CMOS combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level network optimization for low power
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
LP based cell selection with constraints of timing, area, and power consumption
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Probabilistic analysis of large finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Power estimation methods for sequential logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing the maximum power cycles of a sequential circuit
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Memory segmentation to exploit sleep mode operation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic extraction and factorization for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timed shared circuits: a power-efficient design style and synthesis tool
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power distribution topology design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Accurate estimation of combinational circuit activity
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power estimation in sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Transformation and synthesis of FSMs for low-power gated-clock implementation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Estimation of energy consumption in speed-independent control circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Towards a high-level power estimation capability
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
The design and implementation of PowerMill
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Analysis of glitch power dissipation in CMOS ICs
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Explicit evaluation of short circuit power dissipation for CMOS logic structures
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Techniques for fast circuit simulation applied to power estimation of CMOS circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low delay-power product CMOS design using one-hot residue coding
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Determining accuracy bounds for simulation-based switching activity estimation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Guarded evaluation: pushing power management to logic synthesis/design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
An estimation technique to guide low power resynthesis algorithms
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Transistor reordering rules for power reduction in CMOS gates
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Power reduction by gate sizing with path-oriented slack calculation
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Switching activity analysis using Boolean approximation method
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Statistical estimation of sequential circuit activity
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Activity-driven clock design for low power circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Boolean techniques for low power driven re-synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Two-level logic minimization for low power
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Delay optimal partitioning targeting low power VLSI circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimization of post-layout area, delay and power dissipation
Optimization of post-layout area, delay and power dissipation
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Pattern-independent current estimation for reliability analysis of CMOS circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Proud: a fast sea-of-gates placement algorithm
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Optimization of combinational and sequential logic circuits for low power using precomputation
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
POSE: power optimization and synthesis environment
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Glitch analysis and reduction in register transfer level power optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Stochastic sequential machine synthesis targeting constrained sequence generation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
What is the state of the art in commercial EDA tools for low power?
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Re-mapping for low power under tight timing constraints
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
A predictive system shutdown method for energy saving of event-driven computation
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact gate decomposition algorithm for low-power technology mapping
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Power optimization for FPGA look-up tables
Proceedings of the 1997 international symposium on Physical design
A matrix synthesis approach to thermal placement
Proceedings of the 1997 international symposium on Physical design
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Theoretical bounds for switching activity analysis in finite-state machines
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The logarithmic number system for strength reduction in adaptive filtering
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Fast high-level power estimation for control-flow intensive design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
Automated phase assignment for the synthesis of low power domino circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design considerations for battery-powered electronics
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A predictive system shutdown method for energy saving of event-driven computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal low powerX OR gate decomposition
Proceedings of the 37th Annual Design Automation Conference
System level online power management algorithms
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Automating RT-level operand isolation to minimize power consumption in datapaths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Effective low power BIST for datapaths (poster paper)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Power-optimal encoding for DRAM address bus (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Stochastic sequential machine synthesis with application to constrained sequence generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance analysis of a transaction based software system with shutdown
Proceedings of the 2nd international workshop on Software and performance
Proceedings of the conference on Design, automation and test in Europe
Analysis of power-clocked CMOS with application to the design of energy-recovery circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An interleaved dual-battery power supply for battery-operated electronics
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Low power techniques for address encoding and memory allocation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
G-vector: A New Model for Glitch Analysis in Logic Circuits
Journal of VLSI Signal Processing Systems
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Software implementation strategies for power-conscious systems
Mobile Networks and Applications
Efficient global register allocation for minimizing energy consumption
ACM SIGPLAN Notices
Power-optimal encoding for a DRAM address bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic transformation for low-power synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power analysis techniques for SoC with improved wiring models
Proceedings of the 2002 international symposium on Low power electronics and design
Logic Synthesis and Verification
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
Energy Saving Testing of Circuits
Automation and Remote Control
Latency effects of system level power management algorithms
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters
EuroGP '01 Proceedings of the 4th European Conference on Genetic Programming
Routing methodology for minimizing 1nterconnect energy dissipation
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Power management points in power-aware real-time systems
Power aware computing
Algorithm and architecture-level design space exploration using hierarchical data flows
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A Power Minimization Technique for Arithmetic Circuits by Cell Selection
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ILP-based optimization of sequential circuits for low power
Proceedings of the 2003 international symposium on Low power electronics and design
Elements of low power design for integrated systems
Proceedings of the 2003 international symposium on Low power electronics and design
Multivoltage scheduling with voltage-partitioned variable storage
Proceedings of the 2003 international symposium on Low power electronics and design
Power-Conscious Test Synthesis and Scheduling
IEEE Design & Test
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive low-power address encoding techniques using self-organizing lists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
The Interplay of Power Management and Fault Recovery in Real-Time Systems
IEEE Transactions on Computers
Iterative schedule optimization for voltage scalable distributed embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Testability Trade-Offs for BIST Data Paths
Journal of Electronic Testing: Theory and Applications
FIFO power optimization for on-chip networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
RTL Power Optimization with Gate-Level Accuracy
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Estimating the efficiency of collaborative problem-solving, with applications to chip design
IBM Journal of Research and Development
Pseudorandom Test Pattern Generators for Built-in Self-Testing: A Power Reduction Method
Automation and Remote Control
Dynamic Functional Unit Assignment for Low Power
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Quantifying Error in Dynamic Power Estimation of CMOS Circuits
Analog Integrated Circuits and Signal Processing
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Voltage scheduling under unpredictabilities: a risk management paradigm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic functional unit assignment for low power
The Journal of Supercomputing
Multiple voltage and frequency scheduling for power minimization
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Technology mapping for low leakage power and high speed with hot-carrier effect consideration
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low power synthesis of finite state machines with mixed D and T flip-flops
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Energy-delay minimization in nanoscale domino logic
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
Lifetime aware resource management for sensor network using distributed genetic algorithm
Proceedings of the 2006 international symposium on Low power electronics and design
Low-power fanout optimization using MTCMOS and multi-Vt techniques
Proceedings of the 2006 international symposium on Low power electronics and design
Energy-efficient, utility accrual scheduling under resource constraints for mobile embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Minimal energy asynchronous dynamic adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM-SE 45 Proceedings of the 45th annual southeast regional conference
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions
Journal of VLSI Signal Processing Systems
Digital Circuit Optimization via Geometric Programming
Operations Research
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
Using SAT-based techniques in power estimation
Microelectronics Journal
Power optimal MTCMOS repeater insertion for global buses
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Design of an efficient power delivery network in an soc to enable dynamic power management
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level safety mechanisms for safety-critical application-specific low power devices
ICCOMP'05 Proceedings of the 9th WSEAS International Conference on Computers
Energy recovery strategy for low power CMOS circuits design
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
On K-LUT based FPGA optimum delay and optimal area mapping
MACMESE'08 Proceedings of the 10th WSEAS international conference on Mathematical and computational methods in science and engineering
Low-power fanout optimization using multi threshold voltages and multi channel lengths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power-aware, depth-optimum and area minimization mapping of K-LUT based FPGA circuits
WSEAS Transactions on Computers
Unified gated flip-flops for reducing the clocking power in register circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
ILP based approach for input vector controlled (IVC) toggle maximization in combinational circuits
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.