Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions

Authors:
Eun-Gu Jung;Jeong-Gun Lee;Kyoung-Son Jhang;Jeong-A Lee;Dongsoo Har
Affiliations:
Department of Information and Communications, Gwangju Institute of Science and Technology, Gwangju, South Korea 500-712;Computer Laboratory, University of Cambridge, Cambridge, UK CB3 0FD;Department of Computer Engineering, College of Engineering, Chungnam National University, Daejeon, South Korea 305-764;Department of Computer Engineering, Chosun University, Gwangju, South Korea 501-759;Department of Information and Communications, Gwangju Institute of Science and Technology, Gwangju, South Korea 500-712
Venue:
Journal of VLSI Signal Processing Systems
Year:
2007

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Abstract

In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction.