Reliable High-Speed Arbitration and Synchronization
IEEE Transactions on Computers
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Architecture and synthesis for multi-cycle communication
Proceedings of the 2003 international symposium on Physical design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic Production of Globally Asynchronous Locally Synchronous Systems
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
A globally asynchronous locally dynamic system for ASICs and SoCs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
Proceedings of the 30th annual international symposium on Computer architecture
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Aspects of Formal and Graphical Design of a Bus System
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Optimal partitioning of globally asychronous locally synchronous processor arrays
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A method for correcting the functionality of a wire-pipelined circuit
Proceedings of the 41st annual Design Automation Conference
Application adaptive energy efficient clustered architectures
Proceedings of the 2004 international symposium on Low power electronics and design
Mixed-clock issue queue design for energy aware, high-performance cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Enabling on-chip diversity through architectural communication design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An ultra low-power processor for sensor networks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Designing an asynchronous microcontroller using pipefitter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
IEEE Transactions on Computers
Self-timed communication platform for implementing high-performance systems-on-chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
IEEE Transactions on Computers
System level power and performance modeling of GALS point-to-point communication interfaces
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
N-synchronous Kahn networks: a relaxed model of synchrony for real-time systems
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Bioinformatic searches using a single-chip shared-memory multiprocessor
Future Generation Computer Systems
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A Framework for Modeling the Distributed Deployment of Synchronous Designs
Formal Methods in System Design
Reasoning about synchronization in GALS systems
Formal Methods in System Design
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture
Proceedings of the 2006 international symposium on Low power electronics and design
Geometry of synthesis: a structured approach to VLSI design
Proceedings of the 34th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
The SegBus platform - architecture and communication mechanisms
Journal of Systems Architecture: the EUROMICRO Journal
GALS SoC interconnect bus for wireless sensor network processor platforms
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions
Journal of VLSI Signal Processing Systems
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS
ACM SIGARCH Computer Architecture News
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Proceedings of the conference on Design, automation and test in Europe
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
A shared memory module for asynchronous arrays of processors
EURASIP Journal on Embedded Systems
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Coordination Models Orc and Reo Compared
Electronic Notes in Theoretical Computer Science (ENTCS)
Improved ber performance in intra-chip rf/wireless interconnect systems
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Applying CDMA technique to network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Journal of Signal Processing Systems
A trace-based framework for verifiable GALS composition of IPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Proceedings of the 11th Annual Conference Companion on Genetic and Evolutionary Computation Conference: Late Breaking Papers
A modular synchronizing FIFO for NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Exploring Multi-Paradigm Modeling Techniques
Simulation
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Synchronous Estelle: Just Another Synchronous Language?
Electronic Notes in Theoretical Computer Science (ENTCS)
A Survey of Desynchronization in a Polychronous Model of Computation
Electronic Notes in Theoretical Computer Science (ENTCS)
Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
A Verification Approach for GALS Integration of Synchronous Components
Electronic Notes in Theoretical Computer Science (ENTCS)
Bioinformatic searches using a single-chip shared-memory multiprocessor
Future Generation Computer Systems
Power, interface, and integration: handset chipset design issues
IEEE Communications Magazine
Proceedings of the 7th ACM international conference on Computing frontiers
The implementation and evaluation of a low-power clock distribution network based on EPIC
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
A flexible communication scheme for rationally-related clock frequencies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An error-correcting unordered code and hardware support for robust asynchronous global communication
Proceedings of the Conference on Design, Automation and Test in Europe
On the compositionality of round abstraction
CONCUR'10 Proceedings of the 21st international conference on Concurrency theory
A low-area multi-link interconnect architecture for GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Hermes-a - an asynchronous NoC router with distributed routing
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchronous design flow for globally asynchronous locally synchronous systems
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
High performance, energy efficiency, and scalability with GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GALS-Designer: A design framework for GALS software systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation
SSS'11 Proceedings of the 13th international conference on Stabilization, safety, and security of distributed systems
Time aware modelling and analysis of multiclocked VLSI systems
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Analog Integrated Circuits and Signal Processing
DVB-DSNG modem high level synthesis in an optimized latency insensitive system context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A novel hybrid FIFO asynchronous clock domain crossing interfacing method
Proceedings of the great lakes symposium on VLSI
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
Dreams: a framework for distributed synchronous coordination
Proceedings of the 27th Annual ACM Symposium on Applied Computing
From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
Scalable communications for a million-core neural processing architecture
Journal of Parallel and Distributed Computing
Robust evaluation of expressions by distributed virtual machines
UCNC'12 Proceedings of the 11th international conference on Unconventional Computation and Natural Computation
On the formal verification of systems of synchronous software components
SAFECOMP'12 Proceedings of the 31st international conference on Computer Safety, Reliability, and Security
Proceedings of the Conference on Design, Automation and Test in Europe
HEX: scaling honeycombs is easier than scaling clock trees
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Exploring pausible clocking based GALS design for 40-nm system integration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Step persistence in the design of GALS systems
PETRI NETS'13 Proceedings of the 34th international conference on Application and Theory of Petri Nets and Concurrency
Power-aware dynamic memory management on many-core platforms utilizing DVFS
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
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