The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Theoretical Computer Science
Maintaining knowledge about temporal intervals
Communications of the ACM
A Discipline of Programming
DILL: Specifying Digital Logic in LOTOS
FORTE '93 Proceedings of the IFIP TC6/WG6.1 Sixth International Conference on Formal Description Techniques, VI
Specifying Hardware Timing with ET-L OTOS
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
From Action Systems to Modular Systems
FME '94 Proceedings of the Second International Symposium of Formal Methods Europe on Industrial Benefit of Formal Methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Verification of Speed-Dependences in Single-Rail Handshake Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Relative Timing Based Verification of Timed Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Multiclock Esterel: A Reactive Framework for Asynchronous Design
IPDPS '00 Proceedings of the 14th International Symposium on Parallel and Distributed Processing
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Request-Driven GALS Technique for Wireless Communication System
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Interface Design for Rationally Clocked GALS Systems
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Modelling and refinement of an on-chip communication architecture
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
Electronic Notes in Theoretical Computer Science (ENTCS)
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We introduce a formal, time aware framework for modelling and analysis multiclocked VLSI systems. We define a delay calculus framework for our timed formalism, and, furthermore, constraints with which to confine the correctness of the system under development, not only logically but also with respect to timing characteristics. We give an elaborate definition of the timed formalism, Timed Action Systems, and its delay models. With the timing aware formal development framework it is possible to obtain information of multiclocked VLSI systems already at high abstraction levels as our application, a GALS (globally asynchronous, locally synchronous) system, shows.