CAD directions for high performance asynchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Formal verification of pulse-mode asynchronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Concurrency and Hardware Design, Advances in Petri Nets
Automatic Derivation of Timing Constraints by Failure Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Time aware modelling and analysis of multiclocked VLSI systems
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Implementation of handshake components
CSP'04 Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years
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A way to reduce the cost (area) or increase the performance of asynchronous circuits is to make timing assumptions that go beyond the isochronic fork. This, however, results in circuits that are not speed-independent. Such timing assumptions often boil down to imposing that, of two circuit paths that start at the same point, one path is faster than the other. We call speed-dependences of this form chain constraints, and we handle them as processes in a metric-free formalism. This paper applies chain constraints to verify single-rail handshake circuits in the context of their timing assumptions, and to evaluate safety margins for delay fluctuations. We discuss the lessons learned, including decomposition and weakening of extended isochronic fork assumptions, (we typically ignore most of the constituent chain constraints) usage of CMOS cell models in the presence of hazards, and correlations between our discrete-state results and analog simulations.