Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
MOCHA: Modularity in Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of Speed-Dependences in Single-Rail Handshake Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Formal Verification of Safety Properties in Timed Circuits
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Circuits and Technology for Digital's StrongARM(tm) and ALPHA Microprocessors
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Pulse-Mode Macromodular Systems
ICCD '98 Proceedings of the International Conference on Computer Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
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This paper addresses the problem of verifying pulse-mode asynchronous circuits, which combine advantages of different asynchronous design styles. A novel technique is proposed for constructing in a modular manner specifications and functional models of pulse-mode circuits. Case studies show the feasibility of formal verification on the basis of the proposed construction, integrated into an existing technique for verifying synchronous circuits under relative timing constraints at several levels of abstraction.