Theoretical Computer Science
Timing analysis and verification of timed asynchronous circuits
Timing analysis and verification of timed asynchronous circuits
Computer-aided synthesis and verification of gate-level timed circuits
Computer-aided synthesis and verification of gate-level timed circuits
Static timing analysis for self resetting circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Lazy transition systems: application to timing optimization of asynchronous circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Modeling and comparing CMOS implementations of the C-element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Communication and Concurrency
Verification of Speed-Dependences in Single-Rail Handshake Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Automatic Synthesis and Verification of Gate-Level Timed Circuits
Automatic Synthesis and Verification of Gate-Level Timed Circuits
Synthesis of asynchronous controllers for heterogeneous systems
Synthesis of asynchronous controllers for heterogeneous systems
Practical verification and synthesis of low latency asynchronous systems
Practical verification and synthesis of low latency asynchronous systems
CAD directions for high performance asynchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Formal verification of pulse-mode asynchronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Logic Synthesis and Verification
Semi-modular Latch Chains for Asynchronous Circuit Design
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Low-Latency Contro Structures with Slack
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Concurrent computing machines and physical space-time
Mathematical Structures in Computer Science
Asynchronous gate-diffusion-input (GDI) circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Registers for phase difference based logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated interface refinement for compositional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compositional reachability analysis for efficient modular verification of asynchronous designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal specification of a protocol processor
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
TRANSYT: a tool for the verification of asynchronous concurrent systems
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
A compositional minimization approach for large asynchronous design verification
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
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Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facilitating transformations from speed-independent circuits to burst-mode, relative timed, and pulse-mode circuits. Relative timing enables improved performance, area, power and testability in all three cases.