Performance of iterative computation in self-timed rings
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Timing Verification and Optimization for the PowerPCTM Processor Family
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Symbolic functional and timing verification of transistor-level circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
WTA: waveform-based timing analysis for deep submicron circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Verification of Delayed-Reset Domino Circuits Using ATACS
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Self-reset logic for fast arithmetic applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Static timing analysis techniques are widely used to verify the timing behavior of large digital designs implemented predominantly in conventional static CMOS. These techniques, however, are not sufficient to completely verify the dynamic circuit families now finding favor in high-performance designs. In this paper, we describe an approach that extends static timing analysis to a high-performance dynamic CMOS logic family called self-resetting CMOS. Due to the circuit structure employed in SRCMOS, designs naturally decompose into a hierarchy of gates and macros; timing analysis must address and preferably exploit this hierarchy. At the gate level, three categories of constraints on pulse timing arise from considering the effects of pulse width, overlap, and collisions. Timing analysis is performed at the macro level, by a) performing timing tests at macro boundaries and b) using macro-level delay models. We define various macro-level timing tests which ensure that fundamental gate-level timing constraints are satisfied. We extend the standard delay model to handle leading and trailing edges of signal pulses, across-chip variations, tracking of signals, and slow and fast operating conditions. We have developed an SRCMOS timing analyzer based on this approach; the analyzer was implemented as extensions to a standard static timing analysis program, thus facilitating its integration into an existing design system and methodology.