Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
On the models for designing VLSI asynchronous digital systems
Integration, the VLSI Journal
Communications of the ACM
Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Self-timed rings and their application to division
Self-timed rings and their application to division
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An energy-complexity model for VLSI computations
An energy-complexity model for VLSI computations
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Static timing analysis for self resetting circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
A generalized state assignment theory for transformation on signal transition graphs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
Clock-Delayed Domino for Adder and Combinational Logic Desig
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Optimised state assignment for asynchronous circuit synthesis
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
High-Performance Asynchronous Pipeline Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Dynamic Logic in Four-Phase Micropipelines
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Energy and Entropy of VLSI Computations
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
An Asynchronous Low-Power 80C51 Microcontroller
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
High-Speed QDI Asynchronous Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
A doubly-latched asynchronous pipeline
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
High-Speed Non-Linear Asynchronous Pipelines
Proceedings of the conference on Design, automation and test in Europe
The design of high-throughput asynchronous pipelines
The design of high-throughput asynchronous pipelines
GasP Control for Domino Circuits
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous data-driven circuit synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scaling energy per operation via an asynchronous pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper introduces a high-throughput asynchronous pipeline style, called high-capacity (HC) pipelines, targeted to datapaths that use dynamic logic. This approach includes a novel highly-concurrent handshake protocol, with fewer synchronization points between neighboring pipeline stages than almost all existing asynchronous dynamic pipelining approaches. Furthermore, the dynamic pipelines provide 100% buffering capacity, without explicit latches, by means of separate pullup and pulldown control for each pipeline stage: neighboring stages can store distinct data items, unlike almost all existing latchless dynamic asynchronous pipelines. As a result, very high throughput is obtained. Fabricated first-input-first-output (FIFO) designs, in 0.18-µm technology, were fully functional over a wide range of supply voltages (1.2 to over 2.5 V), exhibiting a corresponding range of throughputs from 1.0-2.4 giga items/s. In addition, an experimental finite-impulse response (FIR) filter chip was designed and fabricated with IBM Research, whose speed-critical core used an HC pipeline. The HC pipeline exhibited throughputs up to 1.8 giga items/s, and the overall filter achieved 1.32 giga items/s, thus obtaining 15% higher throughput and 50% lower latency than the fastest previously-reported synchronous FIR filter, also designed at IBM Research.