Automatic Derivation of Timing Constraints by Failure Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Congestion and Starvation Detection in Ripple FIFOs
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Low-Latency Contro Structures with Slack
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Verification of timed circuits with symbolic delays
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
STG Optimisation in the Direct Mapping of Asynchronous Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Asynchronous gate-diffusion-input (GDI) circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
Single-track asynchronous pipeline controller design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Bioinformatic searches using a single-chip shared-memory multiprocessor
Future Generation Computer Systems
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An asynchronous low-power high-performance sequential decoder implemented with QDI templates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NoC Communication Strategies Using Time-to-Digital Conversion
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
A Highly Scalable GALS Crossbar Using Token Ring Arbitration
IEEE Design & Test
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies
Proceedings of the 18th ACM Great Lakes symposium on VLSI
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
Bioinformatic searches using a single-chip shared-memory multiprocessor
Future Generation Computer Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous data-driven circuit synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low latency wormhole router for asynchronous on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Effective contraction of timed STGs for decomposition based timed circuit synthesis
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Timing verification of gasp asynchronous circuits: predicted delay variations observed by experiment
Concurrency, Compositionality, and Correctness
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Clockless physical unclonable functions
TRUST'12 Proceedings of the 5th international conference on Trust and Trustworthy Computing
Slack matching mode-based asynchronous circuits for average-case performance
Proceedings of the International Conference on Computer-Aided Design
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The GasP family of asynchronous circuits provides controls for simple pipelines, for branching and joining pipelines, for round-robin scatter and gather, for data-dependent scatter and gather, and for join on demand through arbitration. The family is designed so that each stage operates at the speed of a three-inverter ring oscillator. Test chips in 0.35 micron technology exhibit throughput in excess of 1.5 giga data items per second (GDI/s). Between GasP pipeline stages a single wire carries both request and acknowledge messages, also recording the FULL or EMPTY state of each pipeline stage. GasP control circuits rely on careful choice of transistor widths to equalize the delay in logic gates. Assurance of uniform gate delays permits use of self-resetting logic forms that have very low logical effort.