Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Clock Synchronization through Handshake Signalling
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Demystifying Data-Driven and Pausible Clocking Schemes
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Early set to zero micro-pipeline
Proceedings of the 11th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing on International Conference on Computer Systems and Technologies
Exploring pausible clocking based GALS design for 40-nm system integration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Pausible clocking based globally-asynchronous locally-synchronous (GALS) system design has been proven a promising approach to SoCs and NoCs. In this paper, we analyze the throughput reduction and synchronization failures introduced by the widely used pausible clocking scheme, and propose an optimized scheme for higher throughput and more reliable GALS design. The local clock generator is improved to minimize the acknowledge latency, and a novel input port is applied to maximize the safe timing region for the clock tree insertion. Simulation results using the IHP 0.13-µm standard CMOS process demonstrate that up to one-third increase in data throughput and an almost doubled safe timing region for clock tree distribution can be achieved in comparison to the traditional pausible clocking scheme.