A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Reconfigurable controllers for synchronization via wagging
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Proceedings of the Conference on Design, Automation and Test in Europe
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VLSI systems are often constructed from a multitude of independently clocked synchronous IP blocks. Unfortunately, while a synchronous design style may produce efficient block level implementations it does little to support their composition. The addition of asynchronous interfaces to each synchronous block is one way to simplify and strengthen their integration. Asynchronous interfaces allow blocks to be composed without the need to consider synchronisation failure rates, permit data-driven operation and provide greater freedom when designing on-chip buses and networks. This paper surveys the significant body of published work in this area. We highlight similarities between schemes that are often concealed by differences in specification or circuit style. We also present new local clock implementations and provide solutions to mitigate the effect of clock-tree insertion delays. The ultimate goal of this work is to permit multi-clock synchronous systems to be composed simply, robustly and efficiently.