Communications of the ACM
Formal program transformations for VLSI circuit synthesis
Formal development programs and proofs
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Predicting Performance of Micropipelines Using Charlie Diagrams
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Optimizing CMOS Implementations of the C-element
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Demystifying Data-Driven and Pausible Clocking Schemes
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Programmable/Stoppable Oscillator Based on Self-Timed Rings
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
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Self-timed rings are a promising approach for designing high-speed serial links or clock generators. This study focuses on the ring stage components - a C-element and an inverter - and compares the performances of different implementations of this component in terms of speed, power consumption and phase noise. We also proposed a new self-timed ring stage - only composed by a C-element with complementary outputs - which allows us to increase the maximum speed of 25% and reduce the power consumption of 60% at the maximum frequency. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics.