Trace theory and systolic computations
Volume I: Parallel architectures on PARLE: Parallel Architectures and Languages Europe
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Communications of the ACM
Specification and automatic verification of self-timed queues
Specification and automatic verification of self-timed queues
On the potential of asynchronous pipelined processors
ACM SIGARCH Computer Architecture News
Four State Asynchronous Architectures
IEEE Transactions on Computers
On the Delay-Sensitivity of Gate Networks
IEEE Transactions on Computers
Design of delay insensitive circuits using multi-ring structures
EURO-DAC '92 Proceedings of the conference on European design automation
Designing an Asynchronous Communications Chip
IEEE Design & Test
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Synthesis of concurrent system interface modules with automatic protocol conversion generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
Timing verification for asynchronous design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Concurrency-oriented optimization for low-power asynchronous systems
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Testing two-phase transition signaling based self-timed circuits in a synthesis environment
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
AMULET1: An Asynchronous ARM Microprocessor
IEEE Transactions on Computers
Clocked and asynchronous instruction pipelines
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph
IEEE Transactions on Computers
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Journal of VLSI Signal Processing Systems
What is the cost of delay insensitivity?
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Self-Timed Carry-Lookahead Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
A Modular Multi-Chip Neuromorphic Architecture for Real-Time Visual Motion Processing
Analog Integrated Circuits and Signal Processing
The design of an asynchronous VHDL synthesizer
Proceedings of the conference on Design, automation and test in Europe
Communicating logic: an alternative embedded stream processing paradigm
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
A New Control Circuit for Asynchronous Micropipelines
IEEE Transactions on Computers
Locally clocked pipelines and dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of asynchronous circuits by synchronous CAD tools
Proceedings of the 39th annual Design Automation Conference
Implementing asynchronous circuits using a conventional EDA tool-flow
Proceedings of the 39th annual Design Automation Conference
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Logic Synthesis and Verification
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
Developing Micropipeline Wavefront Arbiters
IEEE Design & Test
High-Level Modeling and Design of Asynchronous Interface Logic
IEEE Design & Test
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
IEEE Micro
Coping with Latency in SOC Design
IEEE Micro
Salphasic Distribution of Clock Signals for Synchronous Systems
IEEE Transactions on Computers
Hazards, Critical Races, and Metastability
IEEE Transactions on Computers
Self-timed cellular automata and their computational ability
Future Generation Computer Systems - Cellular automata CA 2000 and ACRI 2000
Asynchronous Embryonics with Reconfiguration
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
On the Performance Evaluation of Fully Asynchronous Processor Architectures
MASCOTS '95 Proceedings of the 3rd International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Semi-modular Latch Chains for Asynchronous Circuit Design
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Low-Power Asynchronous A/D Conversion
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Concurrency and Hardware Design, Advances in Petri Nets
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Building Asynchronous Circuits with JBits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Implementing Asynchronous Circuits on LUT Based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Using dynamic domino circuits in self-timed systems
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
DFT for fast testing of self-timed control circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Testing self-timed circuits using partial scan
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A hybrid asynchronous system design environment
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Single-rail handshake circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Hades-towards the design of an asynchronous superscalar processor
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Micronets: a model for decentralising control in asynchronous processor architectures
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Low-latency asynchronous FIFO buffers
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
High-Performance Asynchronous Pipeline Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Dynamic Logic in Four-Phase Micropipelines
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Single-Track Handshake Signaling with Application to Micropipelines and Handshake Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Static Scheduling of Instructions on Micronet-based Asynchronous Processors
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Counterflow Pipeline Based Dynamic Instruction Scheduling
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Fred: An Architecture for a Self-Timed Decoupled Computer
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Control Resynthesis for Control-Dominated Asynchronous Designs
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Coarse-Grain Phased Logic CPU
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Congestion and Starvation Detection in Ripple FIFOs
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Adaptive Pipeline Structures fo Speculation Control
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A New Class of Asynchronous A/D Converters Based on Time Quantization
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Low latency self-timed flow-through FIFOs
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Multi-Chip Neuromorphic Motion Processing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A Macroscopic Behavior Model for Self-Timed Pipeline Systems
Proceedings of the seventeenth workshop on Parallel and distributed simulation
Rapid Prototyping of Networks of Asynchronous Multiple Functional Units
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Fully asynchronous, robust, high-throughput arithmetic structures
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Micropipeline Architecture for Multiplier-less FIR Filters
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A New Methodology for the Design of Asynchronous Digital Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Delay-Insensitive Carry-Lookahead Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Critical hazard free test generation for asynchronous circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An on-line testable UART implemented using IFIS
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ACT: A DFT Tool for Self-Timed Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
AMULET3: A 100 MIPS Asynchronous Embedded Processor
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A hardware design system based on object-oriented principles
EURO-DAC '91 Proceedings of the conference on European design automation
Arbitration-free synchronization
Distributed Computing - Papers in celebration of the 20th anniversary of PODC
Concurrent computing machines and physical space-time
Mathematical Structures in Computer Science
CMOS Structures Suitable for Secured Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 2
ARCS: an architectural level communication driven simulator
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion
Proceedings of the 14th ACM Great Lakes symposium on VLSI
The best of both worlds: the efficient asynchronous implementation of synchronous specifications
Proceedings of the 41st annual Design Automation Conference
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Designing an asynchronous microcontroller using pipefitter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous gate-diffusion-input (GDI) circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
IEEE Transactions on Computers
A clocking technique for FPGA pipelined designs
Journal of Systems Architecture: the EUROMICRO Journal
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-timed communication platform for implementing high-performance systems-on-chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Design of a cell library for asynchronous microengines
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
IEEE Transactions on Computers
A formal approach to designing delay-insensitive circuits
Distributed Computing
A lattice-based framework for the classification and design of asynchronous pipelines
Proceedings of the 42nd annual Design Automation Conference
A Coarse-Grain Phased Logic CPU
IEEE Transactions on Computers
A 120nm low power asynchronous ADC
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
Synthesis methodology for built-in at-speed testing
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An asynchronous architecture for modeling intersegmental neural communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tartan: evaluating spatial computation for whole program execution
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Leveraging protocol knowledge in slack matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Journal of Systems Architecture: the EUROMICRO Journal
NoC Communication Strategies Using Time-to-Digital Conversion
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Test quality analysis and improvement for an embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Integrated Computer-Aided Engineering
Global critical path: a tool for system-level timing analysis
Proceedings of the 44th annual Design Automation Conference
Self-resetting latches for asynchronous micro-pipelines
Proceedings of the 44th annual Design Automation Conference
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique
Journal of Electronic Testing: Theory and Applications
Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Design and analysis of FPGA based self-timed system with specific focus to xilinx FPGAs
ESPOCO'05 Proceedings of the 4th WSEAS International Conference on Electronic, Signal Processing and Control
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Applying CDMA technique to network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic placement of micropipeline standard cells
WSEAS Transactions on Circuits and Systems
Transactions on Petri Nets and Other Models of Concurrency I
Integration, the VLSI Journal
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
A study of asynchronous design methodology for robust CMOS-nano hybrid system design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A modular synchronizing FIFO for NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Speculation in elastic systems
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A low-power delay buffer using gated driver tree
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wave-pipelined intra-chip signaling for on-FPGA communications
Integration, the VLSI Journal
An optimal design method for de-synchronous circuit based on control graph
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
VariPipe: low-overhead variable-clock synchronous pipelines
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A VHDL-based design methodology for asynchronous circuits
WSEAS Transactions on Circuits and Systems
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
Geometry of synthesis III: resource management through type inference
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
The design of a simple asynchronous processor
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
The design of sharing resources for asynchronous systems
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Design of a reconfigurable pulsed quad-cell for cellular-automata-based conformal computing
International Journal of Reconfigurable Computing
Asynchronous computing in sense amplifier-based pass transistor logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constrained asynchronous ring structures for robust digital oscillators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous protocol converters for two-phase delay-insensitive global communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy and performance models for synchronous and asynchronous communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and synthesis of asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A syntax-directed translation for the synthesis of delay-insensitive circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An evaluation for the design of asynchronous systems
WSEAS Transactions on Circuits and Systems
An optimization for the design of a simple asynchronous processor
WSEAS Transactions on Computers
Non-linear asynchronous micro-pipelines
Proceedings of the 12th International Conference on Computer Systems and Technologies
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Relativistic Causality and Clockless Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
C-elements for hardened self-timed circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
A combined arithmetic logic unit and memory element for the design of a parallel computer
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I
Cycle period analysis and optimization of timed circuits
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Properties as processes: their specification and verification
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Implementation of handshake components
CSP'04 Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
Specifying and property checking the AMULET1 address interface
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
A formally based framework for supporting design and analysis of asynchronous hardware systems
1FACS'96 Proceedings of the 1st BCS-FACS conference on Northern Formal Methods
State space reduction for asynchronous micropipelines
1FACS'96 Proceedings of the 1st BCS-FACS conference on Northern Formal Methods
Resilient and adaptive performance logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Communications of the ACM
Clockless physical unclonable functions
TRUST'12 Proceedings of the 5th international conference on Trust and Trustworthy Computing
Design of a low-power embedded processor architecture using asynchronous function units
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Comparison of self-timed ring and inverter ring oscillators as entropy sources in FPGAs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A very high speed true random number generator with entropy assessment
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
Analog Integrated Circuits and Signal Processing
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
Hi-index | 48.27 |
The pipeline processor is a common paradigm for very high speed computing machinery. Pipeline processors provide high speed because their separate stages can operate concurrently, much as different people on a manufacturing assembly line work concurrently on material passing down the line. Although the concurrency of pipeline processors makes their design a demanding task, they can be found in graphics processors, in signal processing devices, in integrated circuit components for doing arithmetic, and in the instruction interpretation units and arithmetic operations of general purpose computing machinery.Because I plan to describe a variety of pipeline processors, I will start by suggesting names for their various forms. Pipeline processors, or more simply just pipelines, operate on data as it passes along them. The latency of a pipeline is a measure of how long it takes a single data value to pass through it. The throughput rate of a pipeline is a measure of how many data values can pass through it per unit time.Pipelines both store and process data; the storage elements and processing logic in them alternate along their length. I will describe pipelines in their complete form later, but first I will focus on their storage elements alone, stripping away all processing logic. Stripped of all processing logic, any pipeline acts like a series of storage elements through which data can pass.Pipelines can be clocked or event-driven, depending on whether their parts act in response to some widely-distributed external clock, or act independently whenever local events permit. Some pipelines are inelastic; the amount of data in them is fixed. The input rate and the output rate of an inelastic pipeline must match exactly. Stripped of any processing logic, an inelastic pipeline acts like a shift register. Other pipelines are elastic; the amount of data in them may vary. The input rate and the output rate of an elastic pipeline may differ momentarily because of internal buffering. Stripped of all processing logic, an elastic pipeline becomes a flow-through first-in-first-out memory, or FIFO. FIFOs may be clocked or event-driven; their important property is that they are elastic.I assign the name micropipeline to a particularly simple form of event-driven elastic pipeline with or without internal processing. The micro part of this name seems appropriate to me because micropipelines contain very simple circuitry, because micropipelines are useful in very short lengths, and because micropipelines are suitable for layout in microelectronic form.I have chosen micropipelines as the subject of this lecture for three reasons. First, micropipelines are simple and easy to understand. I believe that simple ideas are best, and I find beauty in the simplicity and symmetry of micropipelines. Second, I see confusion surrounding the design of FIFOs. I offer this description of micropipelines in the hope of reducing some of that confusion.The third reason I have chosen my subject addresses the limitations imposed on us by the clocked-logic conceptual framework now commonly used in the design of digital systems. I believe that this conceptual framework or mind set masks simple and useful structures like micropipelines from our thoughts, structures that are easy to design and apply given a different conceptual framework. Because micropipelines are event-driven, their simplicity is not available within the clocked-logic conceptual framework. I offer this description of micropipelines in the hope of focusing attention on an alternative transition-signalling conceptual framework.We need a new conceptual framework because the complexity of VLSI technology has now reached the point where design time and design cost often exceed fabrication time and fabrication cost. Moreover, most systems designed today are monolithic and resist mid-life improvement. The transition-signalling conceptual framework offers the opportunity to build up complex systems by hierarchical composition from simpler pieces. The resulting systems are easily modified. I believe that the transition-signalling conceptual framework has much to offer in reducing the design time and cost of complex systems and increasing their useful lifetime. I offer this description of micropipelines as an example of the transition-signalling conceptual framework.Until recently only a hardy few used the transition-signalling conceptual framework for design because it was too hard. It was nearly impossible to design the small circuits of 10 to 100 transistors that form the elemental building blocks from which complex systems are composed. Moreover, it was difficult to prove anything about the resulting compositions. In the past five years, however, much progress has been made on both fronts. Charles Molnar and his colleagues at Washington University have developed a simple way to design the small basic building blocks [9]. Martin Rem's "VLSI Club" at the Technical University of Eindhoven has been working effectively on the mathematics of event-driven systems [6, 10, 11, 19]. These emerging conceptual tools now make transition signalling a lively candidate for widespread use.