The evolution of fault-tolerant computing
The evolution of fault-tolerant computing
Modular Error Detection for Bit-Serial Multiplication
IEEE Transactions on Computers
Communications of the ACM
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Domino logic synthesis using complex static gates
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Technology mapping algorithms for domino logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Advanced Digital Design with the VERILOG HDL
Advanced Digital Design with the VERILOG HDL
A Practical Comparison of Asynchronous Design Styles
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Error Correction Coding: Mathematical Methods and Algorithms
Error Correction Coding: Mathematical Methods and Algorithms
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
Theory of Unidirectional Error Correcting/Detecting Codes
IEEE Transactions on Computers
Monotone Functions in Sequential Circuits
IEEE Transactions on Computers
Reliability and Performance of Error-Correcting Memory and Register Arrays
IEEE Transactions on Computers
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
RSYN: a system for automated synthesis of reliable multilevel circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and synthesis of self-checking VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As VLSI technology continues scaling, increasingly significant parametric variations and increasingly prevalent defects present unprecedented challenges to VLSI design at nanometer scale. Specifically, performance variability has hindered performance scaling, while soft errors become an emerging problem for logic computation at recent technology nodes. In this article, we leverage the existing Totally Self-Checking (TSC)/Strongly Fault-Secure (SFS) logic design techniques, and propose Resilient and Adaptive Performance (RAP) logic for maximum adaptive performance and soft error resilience in nanoscale computing. RAP logic clears all timing errors in the absence of external soft errors, albeit at a higher area/power cost compared with Razor logic. Our experimental results further show that dual-rail static (Domino) RAP logic outperforms alternative Delay-Insensitive (DI) code-based static (Domino) RAP logic with less area, higher performance, and lower power consumption for the large test cases, and achieves an average of 2.29(2.41)× performance boost, 2.12(1.91)× layout area, and 2.38(2.34)× power consumption compared with the traditional minimum area static logic based on the Nangate 45-nm open cell library.