Partially Self-Checking Circuits and Their Use in Performing Logical Operations
IEEE Transactions on Computers
IEEE Transactions on Computers
Monotone Functions in Sequential Circuits
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
IBM Journal of Research and Development
A note on strongly fault-secure sequential circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
On error indication for totally self-checking systems
IEEE Transactions on Computers
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Embedded self-testing checkers for low-cost arithmetic codes
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Highly testable and compact single output comparator
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Finite State Machine Synthesis with Concurrent Error Detection
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Self-Checking Scheme for Very Fast Clocks' Skew Correction
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On the Design of Self-Checking Controllers with Datapath Interactions
IEEE Transactions on Computers
IEEE Transactions on Computers
A Theory of Totally Self-Checking System Design
IEEE Transactions on Computers
Problems of Information Transmission
Implementing high availability memory with a duplication cache
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Computers
RSYN: a system for automated synthesis of reliable multilevel circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Resilient and adaptive performance logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Journal of Electronic Testing: Theory and Applications
Hi-index | 15.00 |
Strongly fault secure logic networks are defined and are shown to include totally self-checking networks as a special case. Strongly fault secure networks provide the same protection against assumed faults as totally self-checking networks, and it is shown that when stuck-at faults are assumed a strongly fault secure network can be easily modified to form a totally self-checking network. A class of strongly fault secure networks is defined in terms of network structure. This structural definition of these "path fault secure" networks facilitates their design and implies other interesting properties. Finally, networks that are strongly fault secure with respect to single stuck-at faults are discussed. A large class of these networks is shown to be easily characterized, and network behavior under nonmodeled faults is considered.