Design of Self-Checking Sequential Machines
IEEE Transactions on Computers
Optimized Synthesis of Concurrently Checked Controllers
IEEE Transactions on Computers
Concurrent Error Detection Using Monitoring Machines
IEEE Design & Test
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Design Diversity Metric and Reliability Analysis for Redundant Systems
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs
IEEE Transactions on Computers
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System
Journal of Electronic Testing: Theory and Applications
Dependable Computing and Online Testing in Adaptive and Configurable Systems
IEEE Design & Test
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Improving On-Line BIST-Based Diagnosis for Roving STARs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
On-Line Monitor Design of Finite-State Machines
Journal of Electronic Testing: Theory and Applications
On Concurrent Error Detection with Bounded Latency in FSMs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation
Journal of Electronic Testing: Theory and Applications
Law of large numbers system design
Nano, quantum and molecular computing
On the Design of Self-Checking Controllers with Datapath Interactions
IEEE Transactions on Computers
Microprocessors & Microsystems
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A comparative study on self-tolerant strategies for hardware immune systems
ICARIS'06 Proceedings of the 5th international conference on Artificial Immune Systems
Self-correction of FPGA-Based control units
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
An adaptive self-tolerant algorithm for hardware immune system
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Circuit Level Concurrent Error Detection in FSMs
Journal of Electronic Testing: Theory and Applications
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A new synthesis technique for designing finite statemachines with on-line parity checking is presented. Theoutput logic and the next-state logic of the finite state machines are checked independently. By checking parity onthe present state instead of the next state, this techniqueallows detection of errors in bistable elements (that werehitherto not detected by many previous techniques) whilerequiring no changes in the original machine specifications. This paper also examines design choices with respect to parity prediction circuits. Two such examinedchoices are the multi-parity-group and the single-parity-group techniques. A new state encoding technique basedon the JEDI program is developed for the synthesis of thenext-state logic with an additional parity output. Synthesisresults produced by our proposed procedure for theMCNC'89 FSM benchmark circuits show on average a25% reduction in literal counts compared to previous techniques.