Logic testing and design for testability
Logic testing and design for testability
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults
Journal of Electronic Testing: Theory and Applications
Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems
Journal of Electronic Testing: Theory and Applications
Defect-oriented test quality assessment using fault sampling and simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On the decline of testing efficiency as fault coverage approaches 100%
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Finite State Machine Synthesis with Concurrent Error Detection
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect level evaluation in an IC design environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
The purpose of this paper is to present a methodology and tools for the design and test of an EN298 compliant ASIC chip for a safety-critical gas burner control system. Safe operation, as far as the critical variable is concerned, is guaranteed in the presence of two simultaneous faults. Emphasis is put on circumventing methodology, EDA (Electronic Design Automation) and foundry limitations and on product certification requirements.