Fault simulation using small fault samples
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
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DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
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Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
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Journal of Electronic Testing: Theory and Applications
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The purpose of this paper is to present a novel methodology forDefect-Oriented (DO) fault sampling, and its implementation in a newextraction tool, lobs (\underline Layout \underline Observer). The methodology is based on the statistics theory, and on the application of the concepts ofestimation of totals over subpopulations and stratified sampling tothe fault sampling problem. The proposed stratified samplingmethodology applies to non-equally probable DO faults, exhibiting a wide range of probabilities ofoccurrence, and leads to confidence intervalssimilar to the ones obtained with equally probable faults. ISCAS benchmark circuits arelaid out and lobs used to ascertain the results, for circuitsup to 100,000 MOS transistors, and extracted DO fault lists of 300,000faults.