IDDQ testing as a component of a test suite: the need for several fault coverage metrics
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Estimating the Quality of Manufactured Digital Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Functional test generation for FSMs by fault extraction
DAC '94 Proceedings of the 31st annual Design Automation Conference
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems
Journal of Electronic Testing: Theory and Applications
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Defect-oriented test quality assessment using fault sampling and simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
EDTC '96 Proceedings of the 1996 European conference on Design and Test
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Quality of Electronic Design: From Architectural Level to Test Coverage
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Testing diagnostics of modern microprocessors with the use of functional models
Automation and Remote Control
System test cost modelling based on event rate analysis
ITC'94 Proceedings of the 1994 international conference on Test
Back annotation of physical defects into gate-level, realistic faults in digital ICs
ITC'94 Proceedings of the 1994 international conference on Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
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The use of stuck-at-fault coverage for estimating overall quality levels is examined. Data from a part tested with both functional and scan tests are analyzed and compared with quality predictions generated by three existing theoretical models. It is shown that reasonable predictions are possible for functional tests, but that scan tests, due to misuse of theoretical equations, produce significantly worse quality levels than predicted.