Freeze!: a new approach for testing sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
Time-efficient automatic test pattern generation systems
Time-efficient automatic test pattern generation systems
Designing Circuits with Partial Scan
IEEE Design & Test
Test Sets and Reject Rates: All Fault Coverages are Not Created Equal
IEEE Design & Test
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Parial Scan Using Reverse Direction Empirical Testability
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
At-Speed Logic BIST Using a Frozen Clock Testing Strategy
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Antirandom testing: a distance-based approach
VLSI Design
RUBASTEM: a method for testing VHDL behavioral models
HASE'04 Proceedings of the Eighth IEEE international conference on High assurance systems engineering
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Random pattern testing methods are known to result in poor fault coverage for most sequential circuits unless costly circuit modifications are made. In this paper, we propose a novel approach to improve the random pattern testability of sequential circuits. We introduce the concept of holding signals at primary inputs and scan flipflops of a partially scanned sequential circuit for a certain length of time, instead of applying a new random vector at each clock cycle. When a random vector is held at the primary inputs of the circuit under test or at the scan flip-flops, the system clock is applied and the primary outputs of the circuit are observed. Information obtained from a testability analysis or test generator is used to determine the number of clock cycles for which each random vector is to be held constant. The method is low cost and the results of our experiment on the benchmark circuits show that it is very effective in providing fault coverage close to the maximum obtainable fault coverage using random patterns with full scan