An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Effectiveness of heuristics measures for automatic test pattern generation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
A Heuristic Measure to Maximize Detected Faults per Test
Journal of Electronic Testing: Theory and Applications
Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
An algorithm to reduce test application time in full scan designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Techniques for improving the efficiency of sequential circuit test generation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Testability forecasting for sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Generation of search state equivalence for automatic test pattern generation
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Methods for Dynamic Test Vector compaction in Sequential Test Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Dynamic test Sequence compaction for Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Deriving Signal Constraints to Accelerate Sequential Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Putting the Squeeze on Test Sequences
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An automatic test pattern generator for large sequential circuits based on genetic algorithms
ITC'94 Proceedings of the 1994 international conference on Test
| Hi-index | 14.99 |
This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of Initial Timeframe Algorithm and correct implementation of a solution to the Previous State Information Problem. The Initial Timeframe Algorithm, one of the most important aspects of the test generator, determines the number of timeframes required to excite the fault for which a test is to be derived and the number of timeframes required to observe the excited fault. Correct determination of the number of timeframes in which the fault should be excited (activated) and observed saves the test generator from performing unnecessary search in the input space. Test generation is unidirectional, i.e., it is done strictly in forward time, and flip-flops in the initial timeframe are never assigned a state that needs to be justified later. The algorithm saves both the good and the faulty machine states after finding a test to aid in subsequent test generation. The Previous State Information Problem, which has often been ignored by existing test generators, is presented and discussed in the paper. Experimental results are presented to demonstrate the effectiveness of the algorithm.