An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Acceleration techniques for dynamic vector compaction
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
A genetic approach to test application time reduction for full scan and partial scan circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Test application time reduction for sequential circuits with scan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
FreezeFrame: compact test generation using a frozen clock strategy
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Putting the Squeeze on Test Sequences
ITC '97 Proceedings of the 1997 IEEE International Test Conference
| Hi-index | 0.00 |
This work addresses two important issues In dynamic teat sequence compaction for sequential circuits: (1) extension of a partially specified test sequence to detect other faults, and (2) reduction in the number of secondary faults that have to he considered white extending a partially specified test sequence. We present a sliding anchor frame technique to specify unspecified signals in a test sequence. Key features of the sliding anchor frame technique are: (1) a test generator deterministically assigns logic values to unspecified signals rather than randomly specify signals as 0 or 1, and (2) every vector in the partially specified test sequence is considered as an anchor vector during the extension of the sequence. This effectively allows observation of fault-effects at any vector in the sequence, which is essential for obtaining test sets of high quality. Experimental results on several sequential circuits show that the sliding anchor frame technique results in significant reductions in test set size and test application cycles.