Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Acceleration techniques for dynamic vector compaction
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Implicit Test Sequences Compaction for Decreasing Test Application Cos
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Dynamic test compaction for synchronous sequential circuits using static compaction techniques
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Methods for Dynamic Test Vector compaction in Sequential Test Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Dynamic test Sequence compaction for Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Automatic test generation using genetically-engineered distinguishing sequences
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
SMART And FAST: Test Generation for VLSI Scan-Design Circuits
IEEE Design & Test
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Dynamic test sequence compaction is an effectivemeans of reducing test application time and often results in higher fault coverages and reduced test generation time as well. A new algorithm for dynamic testsequence compaction is presented that uses genetic techniques to evolve test sequences. Test sequences providedby a test generator and previously evolved sequences already included in the test set are used as seeds in thegenetic population. Significant improvements in test setsize, fault coverage, and test generation time have beenobtained over previous approaches.