Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Asynchronous parallel algorithms for test set partitioned fault simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
A fast, accurate, and non-statistical method for fault coverage estimation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast Static Compaction Algorithms for Sequential Circuit Test Vectors
IEEE Transactions on Computers
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On Non-Statistical Techniques for Fast Fault Coverage Estimation
Journal of Electronic Testing: Theory and Applications
Dynamic state traversal for sequential circuit test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Set Compaction Using Relaxed Subsequence Removal
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
State relaxation based subsequence removal for fast static compaction in sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Putting the Squeeze on Test Sequences
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test generation process. A two-phase algorithm is used during test generation. The first phase activates the target fault, and the second phase propagates the fault effects (FE's) from the flip-flops with assistance from the distinguishing sequences. This strategy improves the propagation of FE's to the primary outputs, and the overall fault coverage is greatly increased. In our new test generator, DIGATE, genetic algorithms are used to derive both activating and distinguishing sequences during test generation. Our results show very high fault coverages for the ISCAS89 sequential benchmark circuits and several synthesized circuits.