Introduction to algorithms
Time-efficient automatic test pattern generation systems
Time-efficient automatic test pattern generation systems
Acceleration techniques for dynamic vector compaction
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Automatic test generation using genetically-engineered distinguishing sequences
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Static compaction using overlapped restoration and segment pruning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
An approach for improving the levels of compaction achieved by vector omission
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Sequence reordering to improve the levels of compaction achievable by static compaction procedures
Proceedings of the conference on Design, automation and test in Europe
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We extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, results in better compaction. Relaxation of a state is possible since not all memory elements in a finite state machine have to be specified for a state transition. The proposed technique has several advantages: (1) test sets that could not be compacted by existing subsequence removal techniques can now be compacted, (2) the size of cycles in a test set can be significantly increased by state relaxation and removal of the larger sized cycles leads to better compaction, (3) only two fault simulation passes are required as compared to trial and re-trial methods that require multiple fault simulation passes, and (4) significantly higher compaction is achieved in short execution times as compared to known subsequence removal methods. Experiments on ISCAS89 sequential benchmark circuits and several synthesized circuits show that the proposed technique consistently results in significantly higher compaction in short execution times.