Sequential Circuit Test Generation Using Dynamic State Traversal

Authors:
Michael S. Hsiao;Elizabeth M. Rudnick;Janak H. Patel
Affiliations:
Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL;Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL;Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

Citing 13
Cited 53

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Abstract

This research was supported in part by the Semiconductor Research Corporation under contract SRC 96-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new method for state justification is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justification. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justification sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus outperforms previous deterministic and simulation-based techniques.