CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Genetics-Based Learning of New Heuristics: Rational Scheduling of Experiments and Generalization
IEEE Transactions on Knowledge and Data Engineering
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
LOCSTEP: A Logic Simulation-Based Test Generation Procedure
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic state traversal for sequential circuit test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Deterministic test pattern generation techniques for sequential circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach
Journal of Electronic Testing: Theory and Applications
SETN '02 Proceedings of the Second Hellenic Conference on AI: Methods and Applications of Artificial Intelligence
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation
ETW '00 Proceedings of the IEEE European Test Workshop
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Application of Genetic Algorithms and BDDs to Functional Testing
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
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This research was supported in part by the Semiconductor Research Corporation under contract SRC 95-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new sequential circuit test generator, ALT-TEST, is described which alternates repeatedly between two phases of test generation. The first phase uses a simulation-based genetic algorithm, while the second phase uses a deterministic algorithm. The fast execution of the first phase combines with the more powerful test sequence generation and redundancy-identification capabilities of the second phase to produce test sets having high fault coverages in low execution times. The effectiveness of the approach is demonstrated on the ISCAS89 sequential benchmark circuits and several synthesized circuits.