Random test generation using concurrent logic simulation
DAC '75 Proceedings of the 12th Design Automation Conference
A Simulation-Based Method for Generating Tests for Sequential Circuits
IEEE Transactions on Computers
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Contest: a concurrent test generator for sequential circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simulation based test generation for scan designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Complexity theory and design automation
DAC '80 Proceedings of the 17th Design Automation Conference
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A proposed hardware fault simulation engine
EURO-DAC '91 Proceedings of the conference on European design automation
On test generation by input cube avoidance
Proceedings of the conference on Design, automation and test in Europe
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Test vector chains for increased targeted and untargeted fault coverage
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Dynamic test compaction for a random test generation procedure with input cube avoidance
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
TOV: sequential test generation by ordering of test vectors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On test generation with test vector improvement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path selection for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Random test generation with input cube avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The problem of generating tests for sequential logic networks has become severe with large-scale integration (LSI). Since the internal gates cannot be tested by direct measurements, it is imperative that a rigorous logic test be developed to ensure quality at the chip level. The sequential complexity of many LSI chips exceeds the practical limitations of the familiar technique of modeling sequential logic for the application of combinational logic test-generation algorithms. Although other approaches, such as pseudo-random pattern generation, have been tried with some success, the pattern count may be quite large. This paper describes a method of test pattern generation that was developed with three objectives: to generate long pattern sequences systematically when needed, to model the sequential logic accurately so that any test generated would be valid, and to focus on assumed faults such as stuck 1 and stuck 0. Also discussed are the strengths and limitations of this method and some comparative results.