CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Scan-Encoded Test Pattern Generation for BIST
Proceedings of the IEEE International Test Conference
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Forming N-detection test sets without test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Forward-looking fault simulation for improved static compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Broadside and skewed-load tests under primary input constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cube is generated at an arbitrary iteration of the test generation process, the test vector improvement step modifies so as to increase the number of yet-undetected target faults that detects. This is done in this paper using a simulation-based process. We show that even if was generated using dynamic test compaction heuristics, it is possible to improve further. When is partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits of. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults).